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Thursday, December 2, 2010

MSBTE:Embedded Systems(9168) CHAPTER 1

CHAPTER 1
IO PORTS AND INTERRUPTS


1.1 8051 Parallel I/O Ports
1.2 Interrupt handling & programming :
1.2.1 Concept of synchronous & asynchronous interrupts,
1.2.2 ISR
1.2.3 Programming external hardware interrupt & Timer interrupt.

Introduction
  • We are living in the Embedded World. We are surrounded with many embedded products and our daily life largely depends on the proper functioning of these gadgets.
  • Television, Radio, CD player of your living room, Washing Machine or Microwave Oven in the kitchen, Card readers, Access Controllers, Palm devices of our work space enable us to do many of our tasks very effectively.
  • Apart from all these, many controllers embedded in the automobiles take care of many important operations.

What is this Embedded System?
  • The computer you use to compose your mails, or create a document or analyze the database is known as the standard desktop computer. These desktop computers are manufactured to serve many purposes and applications. You need to install the relevant software to get the required processing facility.
  • In contrast, embedded controllers carryout a specific work for which they are designed. Most of the time, engineers design these embedded controllers with a specific goal in mind. So these controllers cannot be used in any other place.
  • Theoretically, an embedded controller is a combination of a piece of microprocessor based hardware and the suitable software to undertake a specific task.
  • These days designers have many choices in microprocessors/microcontrollers. Especially, in 8 bit and 32 bit, the available variety really may overwhelm even an experienced designer. Selecting a right microprocessor may turn out as a most difficult first step and it is getting complicated as new devices continue to pop-up very often.
  • In the 8 bit segment, the most popular and used architecture is Intel's 8051. Market acceptance of this particular family has driven many semiconductor manufacturers to develop something new based on this particular architecture. Even after 25 years of existence, semiconductor manufacturers still come out with some kind of device using this 8051 core.


What is the difference between a Microprocessor and Microcontroller?
  • By microprocessor is meant the general purpose Microprocessors such as Intel's X86 family (8086, 80286, 80386, 80486, and the Pentium) or Motorola's 680X0 family (68000, 68010, 68020, 68030, 68040, etc).
  • These microprocessors contain no RAM, no ROM, and no I/O ports on the chip itself. For this reason, they are commonly referred to as general-purpose Microprocessors.
  • A system designer using a general-purpose microprocessor such as the Pentium or the 68040 must add RAM, ROM, I/O ports, and timers externally to make them functional. Although the addition of external RAM, ROM, and I/O ports makes these systems bulkier and much more expensive, they have the advantage of versatility such that the designer can decide on the amount of RAM, ROM and I/O ports needed to fit the task at hand.
  • This is not the case with Microcontrollers. A Microcontroller has a CPU (a microprocessor) in addition to a fixed amount of RAM, ROM, I/O ports, and a timer all on a single chip.
  • In other words, the processor, the RAM, ROM, I/O ports and the timer are all embedded together on one chip.
  • The fixed amount of on-chip ROM, RAM, and number of I/O ports in Microcontrollers makes them ideal for many applications in which cost and space are critical.
  • In many applications, for example a TV remote control, there is no need for the computing power of a 486 or even an 8086 microprocessor. These applications most often require some I/O operations to read signals and turn on and off certain bits.

Microcontrollers for Embedded Systems
·        Microprocessors and Microcontrollers are widely used in embedded system products. An embedded system product uses a microprocessor (or Microcontroller) to do one task only.
·         A printer is an example of embedded system since the processor inside it performs one task only; namely getting the data and printing it.
·        A PC can be used for any number of applications such as word processor, print-server, bank teller terminal, Video game, network server, or Internet terminal. Software for a variety of applications can be loaded and run.
·        The reason a pc can perform variety of  tasks is that it has RAM memory and an operating system that loads the application software into RAM memory and lets the CPU run it.
·        In an Embedded system, there is only one application software that is typically burned into ROM.
·         An x86 PC contains or is connected to various embedded products such as keyboard, printer, modem, disk controller, sound card, CD-ROM drives, mouse, and so on. Each one of these peripherals has a Microcontroller inside it that performs only one task.
·        For example, inside every mouse there is a Microcontroller to perform the task of finding the mouse position and sending it to the PC. Table 1-1 lists some embedded products.
                                                                                     


Home Appliance
    Office
       Automobiles
Instrumentation

Intercom

Telephones

Engine control

Climate control

Washing Machines

Computers

Air bag

Keyless Entry

TV's

Fax Machine

ABS (Automatic Brake System)

Security systems

DVD/CD player

Laser Printer

Transmission control
















8051 Parallel I/O Ports
  • There are four ports P0, P1, P2 and  P3 each  use  8 pins,  making  them 8-bit  ports.
  •  All the ports latches upon RESET are one, If intermittently zero is written on port then to use any of these ports as an input port, it must be programmed to one.
  • All four ports in the 80C51 are bidirectional. Each consists of a latch (Special Function Register P0 ,P1,P2 and  P3), an output driver, and an input buffer.
  •  All the port latches in the 80C51 have 1’s written to them by the reset function. If a 0 is subsequently written to a port latch, it can be re configured as an input by writing a 1 to it.
  
Port 0:
Port 0 occupies a total of 8 pins (pins 32-39) . It can be used for input or output. 
Above figure shows a functional diagram of a typical bit latch and I/O buffer in port 1.
  1. The bit latch (one bit in the port’s SFR) is represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a “write to latch” signal from the CPU.
  2. The Q output of the flip-flop is placed on the internal bus in response to a“read latch” signal from the CPU.
  3. The level of the port pin itself is placed on the internal bus in response to a “read pin” signal from the CPU.
  4. Some instructions that read a port activate the “read latch” signal, and others activate the “read latch” signal, and others activate the “read pin” signal.
  5. Port 0 differs in not having internal pull-ups. The pull-up FET in the P0 output driver is used only when the Port is emitting 1’s during external memory accesses. Otherwise the pull-up FET is off which forms open drain collector.
  6. To use the pins of port 0 as both input and output ports, each pin must be connected externally to a 10K ohm pull-up resistor as shown in figure below.
  7. The output drivers of Ports 0 are switchable to an internal ADDR/DATA bus by an internal CONTROL signal for use in external memory accesses.
  8. To be used as an input, the port bit latch must contain a 1, which turns off the output driver FET.
Dual role of port 0:
  • Port 0 is also designated as AD0-AD7, allowing it to be used for both address and data. When connecting an 8051/31 to an external memory, port 0 provides both address and data.
  • The 8051 multiplexes address and data through port 0 to save pins. ALE indicates if P0 has address or data. When ALE = 0, it provides data D0-D7, but when ALE =1 it has address and data with the help of a 74LS373 latch.


Port 1: Port 1 occupies a total of 8 pins (pins 1 through 8). It can be used as input or output.
  1. The bit latch is represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a “write to latch” signal from the CPU.
  2. The Q output of the flip-flop is placed on the internal bus in response to a“read latch” signal from the CPU.
  3. The level of the port pin itself is placed on the internal bus in response to a “read pin” signal from the CPU.
  4. Some instructions that read a port activate the “read latch” signal, and others activate the “read latch” signal, and others activate the “read pin” signal.
  5. In contrast to port 0, this port does not need any pull-up resistors since it already has pull-up resistors internally.


Port 2 : Port 2 occupies a total of 8 pins (pins 21- 28). It can be used as input or output.
  1. The bit latch is represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a “write to latch” signal from the CPU.
  2. The Q output of the flip-flop is placed on the internal bus in response to a“read latch” signal from the CPU.
  3. The level of the port pin itself is placed on the internal bus in response to a “read pin” signal from the CPU.
  4. Some instructions that read a port activate the “read latch” signal, and others activate the “read latch” signal, and others activate the “read pin” signal.
  5. This port does not need any pull-up resistors since it already has pull-up resistors internally.
  6. The output drivers of Ports 0 are switchable to an internal ADDR bus by an internal CONTROL signal for use in external memory accesses.

Dual role of port 2:
·        Port 2 must be used along with P0 to provide the 16-bit address for the external memory. As shown in pin configuration 8051, port 2 is also designed as A8-A15, indicating the dual function.
·        Since an 8051 is capable of accessing 64K bytes of external memory, it needs 16 bits of the address. While P0 provides the lower 8 bits via A0-A7, it is the job of P2 to provide bits A8-A15 of the address.
·        In other words, when 8031 is connected to external memory, P2 is used for the upper 8 bits of the 16 bit address, and it cannot be used for I/O.
·        Ports 0 and 2 may not be used as general purpose I/O when being used as the ADDR/DATA BUS.
Port 3
Port 3 occupies a total of 8 pins, pins 10 through 17. It can be used as input or output. Port 3 has the additional function of providing important signals as shown in figure below.
  1. The bit latch is represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a “write to latch” signal from the CPU.
  2. The Q output of the flip-flop is placed on the internal bus in response to a“read latch” signal from the CPU.
  3. The level of the port pin itself is placed on the internal bus in response to a “read pin” signal from the CPU.
  4. Some instructions that read a port activate the “read latch” signal, and others activate the “read latch” signal, and others activate the “read pin” signal.
  5. This port does not need any pull-up resistors since it already has pull-up resistors internally.
  6. If a P3 bit latch contains a 1, then the output level is controlled by the signal labelled “alternate output function.” The actual P3.X pin level is always available to the pin’s alternate input function.


Read-modify-write feature:
·        The ports in the 8051 can be accessed by the read-modify-write technique. This feature saves many lines of code by combining in a single instruction all three actions of (1) reading the port, (2) modifying it, and (3) writing to the port.


Single bit addressability of ports: 
·        There are times that we need to access only 1 or 2 bits of the port instead of the entire 8 bits. A powerful feature of 8051 I/O ports is their capability to access individual bits of the port without altering the rest of the bits in that port.

Interrupt handling & programming

Interrupts

·         An interrupt is usually defined as an event that alters the sequence of instructions executed by a processor. Such events correspond to electrical signals generated by hardware circuits both inside and outside the CPU chip.
Interrupts are often divided into synchronous and asynchronous interrupts:
·         Synchronous interrupts are produced by the CPU control unit while executing instructions and are called synchronous because the control unit issues them only after terminating the execution of an instruction.
·         Asynchronous interrupts are generated by other hardware devices at arbitrary times with respect to the CPU clock signals.
·         Intel microprocessor manuals designate synchronous and asynchronous interrupts as exceptions and interrupts, respectively.
·          Interrupts are issued by interval timers and I/O devices; for instance, the arrival of a keystroke from a user sets off an interrupt.
·         Exceptions, on the other hand arrive after the execution of an instruction, and  are caused either by programming errors or by anomalous conditions. Eg. Page fault or when the cpu try to devide a number by 0.
·         A trap is a kind of exceptions, whose main purpose is for debugging
·         A software interrupt (Programmed Exceptions) occur at the request of the programmer. They are used to implement system calls. Software interrupt is a considered to be an exception (because they are synchronous).

Interrupt Service Routine ( ISR)
  • Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device.
  • The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.
  •  For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler.
  • When an interrupt is invoked, the microcontroller runs the interrupt service routine.
  •  For every interrupt, there is a fixed location in memory that holds the address of its ISR .
  • The group of memory locations set aside to hold the addresses of ISRs is called interrupt vector table.

Upon activation of an interrupt, the microcontroller goes through the following steps:
1.      It finishes the instruction it is executing and saves the address of the next instruction (PC) on the stack
2.      It also saves the current status of all the interrupts internally (i.e: not on the stack).
3.      It jumps to a fixed location in memory, called the interrupt vector table, that holds the address of the ISR.
4.       The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it. It starts to execute the interrupt service subroutine until it reaches the last instruction of the subroutine which is RETI (return from interrupt)
5.      Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted. First, it gets the program counter (PC) address from the stack by popping the top two bytes of the stack into the PC.Then it starts to execute from that address.


8051 INTERRUPTS


There are five interrupt sources for the 8051. Since the main RESET input can also be considered as an interrupt, six interrupts can be listed as follows:

Interrupt                                                           Vector address

-----------------------------------------------------------------------------------
RESET                                                 0000h

External interrupt 0                                           0003h

Timer/counter 0                                                000Bh

External interrupt 1                                           0013h

Timer/counter 1                                                001Bh
Serial port                                                        0023h

Enabling and disabling an interrupt
  • Upon reset, all interrupts are disabled (masked), meaning that none will be responded to by the microcontroller if they are activated.
  • The interrupts must be enabled by software in order for the microcontroller to respond to them.
  • There is a register called IE (interrupt enable) this is responsible for enabling (unmasking) and disabling (masking) the interrupts. The Interrupt Enable, IE, register is an SFR register at location A8h in Internal RAM.
  • Above figure shows the IE register. Note that IE is a bit-addressable register. From Figure  notice that bit D7 in the IE register is called EA (enable all).
  • This must be set to 1 in order for the rest of the register to take effect. D6 is unused. D5 is used by the 8052 for Timer 2 interrupt.  The D4 bit is for the serial interrupt, and so on.



Steps in enabling an interrupt
To enable an interrupt, we take the following steps:
  1. Bit D7 of the IE register (EA) must be set to high to allow the rest of register to take effect.
  2. If EA = 1, interrupts are enabled and will be responded to if their corresponding bits in IE are high. If EA = 0, no interrupt will be responded to, even if the associated bit in the IE register is high.

Programming External Hardware Interrupts
·        We will concentrate on the external interrupts for now, and later we will examine the other interrupt sources.
·        The 8051 has two external hardware interrupts PIN 12 (P3.2) and Pin 13 (P3.3) of the 8051, designated as INT0  and INT1 are used as external hardware interrupts.
·         Here’s a brief look at some of the register bits which will be used to set up the interrupts. The EA bit will enable all interrupts (when set to 1) and the individual interrupts must also be enabled.


  • For example, if we want to enable the two external interrupts we would use the instruction:
MOV  IE, #10000101B

  • Each of the two external interrupt sources can be defined to trigger on the external signal, either on a negative going edge or on a logic low level state. i.e. it can be either
    1. Edge triggered
    2. Level triggered.

Edge Triggered Interrupt:
  • Upon reset 8051 makes INT0 and INT1 low l Level-Triggered Interrupt. To make them Edge -Triggered Interrupt, we must program the IT0 and IT1 bits of the TCON Register.
  • In negative edge trigger mode, the interrupt in-service flag IE0 and IE1 of TCON registers are set while the interrupts are  being serviced and  automatically cleared by hardware once interrupts are processed.
  • The TCON register is another SFR register and is located at location 88h in Internal RAM. (The other bits in the TCON register will be described later in the context of the hardware Timer/Counters.)

  • The TCON register holds, among other bits, the IT0 and IT1 flag bits that determine level- or edge-triggered mode of the hardware interrupt
  •  IT0 and IT1 are bits D0 and D2 of the TCON register  They are also referred to as TCON.0 and TCON.2 since the TCON register is bit addressable
  • To define negative edge triggering for the two external interrupts use instructions as follows:
SETB TCON.0                        ; negative edge trigger for interrupt 0
SETB TCON.2                        ; negative edge trigger for interrupt 1
  • In edge-triggered interrupts the external source must be held high for at least one machine cycle, and then held low for at least one machine cycle
  • The falling edge of pins INT0 and INT1 are latched by the 8051 and is held by the TCON register bits D1 and D3 respectively. ( IE0 and IE1)
  • TCON.1 and TCON.3 bits of TCON register function as interrupt-in-service flags. High status on these flags indicates that the interrupt is being serviced now and on this INTn pin, and no new interrupt will be responded to until this service is finished.
  • These flags are cleared by the CPU once the ISRs are processed. There is no need for instruction CLR TCON.1 before RETI in the ISR associated with INT0 or INT1.
Level Triggered Interrupt:
  • In the level-triggered mode, INT0 and INT1 pins are normally high. If a low-level signal is applied to them, it triggers the interrupt then the microcontroller stops whatever it is doing and jumps to the interrupt vector table to service that interrupt.
  • The low-level signal at the INT pin must be removed before the execution of the last instruction of the ISR, RETI; otherwise, another interrupt will be generated.
  • This is the default mode upon reset of the 8051.


Programming Timer Interrupts

Roll-over timer flag and interrupt
  • The timer flag (TF) is raised when the timer rolls over.
  • In polling TF, we have to wait until the TF is raised. The problem with this method is that the microcontroller is tied down while waiting for TF to be raised, and cannot do any thing else.
  • Using interrupts solves this problem and avoids tying down the controller.
  •  If the timer interrupt in the IE register is enabled, whenever the timer rolls over, TF is raised, and the microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the ISR. In this way, the microcontroller can do other things until it is notified.
  • Steps in programming Timer Interrupt
1.      Bit D7 of the IE register (EA) must be set to high.
2.      Enable bit D1(ET0) and  D3(ET1) of IE register to enable Timer0  and Timer1 interrupt respectively.
3.      Enter Timer0 and Timer1 ISR address in Interrupt vector table locations 000Bh and 001Bh respectively.
Interrupt priority level structure

·        An individual interrupt source can be assigned one of two priority levels.  The Interrupt Priority, IP, register is an SFR register used to program the priority level for each interrupt source.
·        A logic 1 specifies the high priority level while a logic 0 specifies the low priority level.


  • An ISR routine for a high priority interrupt cannot be interrupted. An ISR routine for a low priority interrupt can be interrupted by a high priority interrupt, but not by a low priority interrupt.
  • If two interrupt requests, at different priority levels, arrive at the same time then the high priority interrupt is serviced first.
  • If two, or more, interrupt requests at the same priority level arrive at the same time then the interrupt to be serviced is selected based on the order shown below.
  • Note, this order is used only to resolve simultaneous requests. Once an interrupt service begins it cannot be interrupted by another interrupt at the same priority level.

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